Field of the Disclosure
Embodiments of the present disclosure generally relate to the fabrication of integrated circuits and particularly to an apparatus and method for reducing change created within semiconductor devices due to their exposure to various types of radiation during a formation or inspection process.
Description of the Related Art
The integrated circuit (IC) market is continually demanding greater memory capacity, faster switching speeds, and smaller feature sizes. Reducing the size of integrated circuits (ICs) results in improved performance, increased capacity and/or reduced cost. Each size reduction, or IC processing node shift, requires more sophisticated techniques to form the various components within the ICs. As IC devices become smaller the physical integrity and dimensional stability of structures formed within the IC device becomes much more challenging to reliably maintain when they are exposed to various forms of radiation provided energy during typical IC forming and inspection processes. For example, photolithography and etching processes are commonly used to pattern various layers formed in the IC device, such as a photoresist layer, spin-on-carbon (SOC) layer, BARC layer and hard mask layers. The exposure of these various layers to the energy generated during the photolithography and etching operations, such as RF energy and electromagnetic radiation used during inspection or post-processing operations can alter, change or adversely affect the properties of the formed IC layers and structures.
One aspect of the IC device structure that can be readily affected during the IC fabrication process, due to the exposure to one or more forms of energy, is line width roughness (LWR) or line edge roughness (LER) that are created in a photolithographic process. As known in the art, LWR is defined as the excessive variations in the width of the patterned photoresist feature formed after the unexposed portions of the photoresist are stripped from the substrate in, for example, a negative resist type lithography process. If the variations occur on the side surface of the photoresist relief or feature the variation is known as LER. An increase in roughness or variations in LWR or LER due to the exposure to various forms of energy during processing is disadvantageous, as the increased roughness variation may be transferred onto various features during the subsequent etching process, and thus ultimately into the formed IC circuit. The variations become more significant as the feature size of the photoresist relief or trenches is decreased. For 32 nm devices variations of 4 nm or larger have been observed. Because the geometrical shape of a patterned resist feature, including line roughness effects (e.g., LWR and LER), is transferred from a patterned photoresist layer to an underlying permanent layer of a device during patterning of the underlying layer, LWR and LER can limit the ability to form devices of acceptable quality for dimensions below about 100 nm. Such variations may lead to non-uniform circuits and ultimately device degradation or failure.
Therefore, as devices shrink to smaller dimensions, current IC fabrication processes are challenged to create devices that can be formed with the required physical and structural properties, and desired critical dimensions (CD). Therefore, there is a need for new apparatuses and methods that can reduce the damaging effects of radiation provided during an IC fabrication process on the physical properties, electrical properties and dimensional stability of structures formed within an IC on a substrate.